1. Field of the Invention
The present invention relates to a static induction transistor (SIT) and in particular to a high-frequency recess gate type or side gate type static induction transistor having high output power.
2. Description of the Related Art
An SIT according to a related art will be described with reference to FIG. 20. FIG. 20 (A) shows a surface gate type SIT, which includes an n.sup.+ substrate 101 serving as a drain region, an n epitaxial layer 102 serving as a channel region provided over the substrate 101, an n.sup.+ source region 103 and a p.sup.+ gate region 104 that are formed on the surface of the n epitaxial layer 102. According to such a surface gate structure, a gate resistance is reduced to improve the high-frequency characteristics. The surface gate type SIT operating at up to about 1 GHz has been provided. Since the p.sup.+ gate region 104 having the diffusion depth of 2-3 .mu.m or more is provided, the breakdown voltage having 200-300 V can be obtained when the thickness of the n epitaxial layer 102 is 20 .mu.m, and similarly the breakdown voltage having 600 V can be provided when the thickness of the n epitaxial layer 102 is 6 .mu.m.
A recess gate type SIT and a side gate type SIT shown in FIGS. 20 (B) and (C) have been proposed as structures for furthermore improving the high-frequency characteristics. In the recess gate type SIT, a groove 105 is formed in the n epitaxial layer 102, and a p.sup.+ gate region 106 is provided on a bottom of the groove 105. In the side gate type SIT, a p.sup.+ gate region 108 is formed in both corners of a groove 107 made in the n epitaxial layer 102. Since these SITs have reduced gate-source capacitance C.sub.gs and gate-drain capacitance C.sub.gd as compared with the surface gate type SIT, the power gain can be increased to almost the upper limit of the UHF band. If the n epitaxial layer 102 is about 6-10 .mu.m thick, for example, in the recess gate type SIT, the power gain at 1-3 GHz is 7-10 dB and a device operable at several GHz as the maximum oscillation frequency f.sub.max at which the gain becomes 1 (0 dB) can be provided.
To enhance the high-frequency characteristics, the gate-source capacitance C.sub.gs and gate-drain capacitance C.sub.gd may be reduced. For reducing C.sub.gd, the diffusion depth Xj of the p.sup.+ gate region 106 may be made shallow. Since C.sub.gd increases inversely with the distance between the gate region and the drain region, the n epitaxial layer 102 may be made thick to reduce C.sub.gd. However, if the n epitaxial layer 102 is made thick, the gain is reduced due to the transit time effect produced by the fact that electrons flow from the source region to the drain region. Therefore, C.sub.gd and f.sub.max have a trade-off relation with respect to the thickness of the n epitaxial layer 102.
In order to increase gate-to-drain breakdown voltage BV.sub.gd, Xj may be increased. However, the distance between the gate region and the drain region is decreased to increase C.sub.gd. That is, BV.sub.gd and C.sub.gd have a trade-off relation with respect to the diffusion thickness Xj of the p.sup.+ gate region 106. As described above, the high-frequency characteristics are strongly concerned with the breakdown voltage. BV.sub.gd is a reverse breakdown voltage of a pn junction between the gate and drain regions, thereby determining the maximum voltage (breakdown voltage) applicable to the drain region.
By the way, the actual BV.sub.gd of the recess gate type SIT is lower than the theoretical breakdown voltage determined by a flat junction portion. Applying a voltage to the pn junction between the gate and drain regions until the breakdown voltage, the surface of the SIT was then observed by an infrared radiation microscope. It was found that a temperature rise occurs at the outermost peripheral portion of the p.sup.+ gate region 106, whereby the breakdown voltage is lowered at a spherical or cylindrical junction portion produced at the outermost peripheral portion rather than the flat junction portion (the portion at which theoretical breakdown voltage is obtained) between the gate and drain regions.
Since the output power in the SITs is increased in proportion to the product of drain voltage and drain current, it is optimum design to provide the theoretical breakdown voltage determined by the thickness between the gate and drain regions without lowering the high-frequency characteristics in order to realize high frequency and large output power devices. However, the actual BV.sub.gd is lower than the theoretical breakdown voltage and, therefore, it is necessary to increase the BV.sub.gd to the theoretical breakdown voltage in order to provide the high frequency and large output power recess gate type SIT. The same statement is true for the side gate type SIT.
Next, the structure of the gate and the source electrodes in the SITs will be schematically described with reference to FIG. 21 (A). P.sup.+ gate and n.sup.+ source regions are disposed in parallel within a region enclosed with a broken line (element portion 120), and gate electrodes 108 and source electrodes 109 are provided on the p.sup.+ gate and n.sup.+ source regions, respectively. An aluminum (Al) gate contact pad 110 and an aluminum (Al) surface contact pad 111 are formed on regions outside the element portion 120. Right-upward oblique lines are indicatively drawn in a connection portion 112 between the gate contact pad 110 and each of the gate electrodes 108, and left-downward oblique lines are drawn in a connection portion 113 between the source contact pad 111 and each of source electrodes 109. As shown in FIG. 21 (B), the gate contact pad 110 is provided on an oxide film 114 formed on the n epitaxial layer 102. Likewise, although not shown, the source contact pad 111 is also formed on the oxide film 114. In such a pad structure, the breakdown voltage between the gate and drain regions is about 200-300 V although it depends on the thickness and quality of the oxide film underlying each Al pad.
Further, an SIT is constituted by one element portion. Since the drain current is proportional to the total source length, the area of the element portion 120 may be increased to increase the total source length in order to increase the drain current. However, resistance and inductance of the source and gate regions are increased as the area of element portion 120 is increased; particularly when the SIT is used in a microwave band, the operating conditions of the device will be greatly affected by the resistance and inductance. Therefore, there is a limit for increasing the area of the element portion.